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Restored generic (non-SIMD) code

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This commit is contained in:
Brian Harris
2013-05-29 13:12:13 -05:00
parent be311f42e1
commit 9c37079c16
23 changed files with 3328 additions and 24 deletions
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22
neo/idlib/math/VecX.h
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@@ -213,7 +213,7 @@ ID_INLINE idVecX idVecX::operator-() const {
idVecX m;
m.SetTempSize( size );
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
ALIGN16( unsigned int signBit[4] ) = { IEEE_FLT_SIGN_MASK, IEEE_FLT_SIGN_MASK, IEEE_FLT_SIGN_MASK, IEEE_FLT_SIGN_MASK };
for ( int i = 0; i < size; i += 4 ) {
_mm_store_ps( m.p + i, _mm_xor_ps( _mm_load_ps( p + i ), (__m128 &) signBit[0] ) );
@@ -233,7 +233,7 @@ idVecX::operator=
*/
ID_INLINE idVecX &idVecX::operator=( const idVecX &a ) {
SetSize( a.size );
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
for ( int i = 0; i < a.size; i += 4 ) {
_mm_store_ps( p + i, _mm_load_ps( a.p + i ) );
}
@@ -254,7 +254,7 @@ ID_INLINE idVecX idVecX::operator+( const idVecX &a ) const {
assert( size == a.size );
m.SetTempSize( size );
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
for ( int i = 0; i < size; i += 4 ) {
_mm_store_ps( m.p + i, _mm_add_ps( _mm_load_ps( p + i ), _mm_load_ps( a.p + i ) ) );
}
@@ -276,7 +276,7 @@ ID_INLINE idVecX idVecX::operator-( const idVecX &a ) const {
assert( size == a.size );
m.SetTempSize( size );
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
for ( int i = 0; i < size; i += 4 ) {
_mm_store_ps( m.p + i, _mm_sub_ps( _mm_load_ps( p + i ), _mm_load_ps( a.p + i ) ) );
}
@@ -295,7 +295,7 @@ idVecX::operator+=
*/
ID_INLINE idVecX &idVecX::operator+=( const idVecX &a ) {
assert( size == a.size );
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
for ( int i = 0; i < size; i += 4 ) {
_mm_store_ps( p + i, _mm_add_ps( _mm_load_ps( p + i ), _mm_load_ps( a.p + i ) ) );
}
@@ -315,7 +315,7 @@ idVecX::operator-=
*/
ID_INLINE idVecX &idVecX::operator-=( const idVecX &a ) {
assert( size == a.size );
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
for ( int i = 0; i < size; i += 4 ) {
_mm_store_ps( p + i, _mm_sub_ps( _mm_load_ps( p + i ), _mm_load_ps( a.p + i ) ) );
}
@@ -337,7 +337,7 @@ ID_INLINE idVecX idVecX::operator*( const float a ) const {
idVecX m;
m.SetTempSize( size );
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
__m128 va = _mm_load1_ps( & a );
for ( int i = 0; i < size; i += 4 ) {
_mm_store_ps( m.p + i, _mm_mul_ps( _mm_load_ps( p + i ), va ) );
@@ -356,7 +356,7 @@ idVecX::operator*=
========================
*/
ID_INLINE idVecX &idVecX::operator*=( const float a ) {
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
__m128 va = _mm_load1_ps( & a );
for ( int i = 0; i < size; i += 4 ) {
_mm_store_ps( p + i, _mm_mul_ps( _mm_load_ps( p + i ), va ) );
@@ -551,7 +551,7 @@ idVecX::Zero
========================
*/
ID_INLINE void idVecX::Zero() {
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
for ( int i = 0; i < size; i += 4 ) {
_mm_store_ps( p + i, _mm_setzero_ps() );
}
@@ -567,7 +567,7 @@ idVecX::Zero
*/
ID_INLINE void idVecX::Zero( int length ) {
SetSize( length );
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
for ( int i = 0; i < length; i += 4 ) {
_mm_store_ps( p + i, _mm_setzero_ps() );
}
@@ -611,7 +611,7 @@ idVecX::Negate
========================
*/
ID_INLINE void idVecX::Negate() {
#ifdef VECX_SIMD
#if defined(ID_WIN_X86_SSE_INTRIN) && defined(VECX_SIMD)
ALIGN16( const unsigned int signBit[4] ) = { IEEE_FLT_SIGN_MASK, IEEE_FLT_SIGN_MASK, IEEE_FLT_SIGN_MASK, IEEE_FLT_SIGN_MASK };
for ( int i = 0; i < size; i += 4 ) {
_mm_store_ps( p + i, _mm_xor_ps( _mm_load_ps( p + i ), (__m128 &) signBit[0] ) );