mirror of
https://github.com/love2d/megasource.git
synced 2026-08-20 04:30:45 +02:00
Update LuaJIT to the latest 2.1.0 source (0bee44c)
This commit is contained in:
Alex Szpakowski
+146
-39
@@ -13,10 +13,17 @@
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if (rex != 0x40) *--(p) = rex; }
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#define FORCE_REX 0x200
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#define REX_64 (FORCE_REX|0x080000)
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#define VEX_64 0x800000
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#else
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#define REXRB(p, rr, rb) ((void)0)
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#define FORCE_REX 0
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#define REX_64 0
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#define VEX_64 0
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#endif
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#if LJ_GC64
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#define REX_GC64 REX_64
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#else
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#define REX_GC64 0
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#endif
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#define emit_i8(as, i) (*--as->mcp = (MCode)(i))
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@@ -31,6 +38,13 @@ static LJ_AINLINE MCode *emit_op(x86Op xo, Reg rr, Reg rb, Reg rx,
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MCode *p, int delta)
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{
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int n = (int8_t)xo;
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if (n == -60) { /* VEX-encoded instruction */
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#if LJ_64
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xo ^= (((rr>>1)&4)+((rx>>2)&2)+((rb>>3)&1))<<13;
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#endif
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*(uint32_t *)(p+delta-5) = (uint32_t)xo;
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return p+delta-5;
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}
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#if defined(__GNUC__)
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if (__builtin_constant_p(xo) && n == -2)
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p[delta-2] = (MCode)(xo >> 24);
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@@ -85,26 +99,17 @@ static int32_t ptr2addr(const void *p)
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#define ptr2addr(p) (i32ptr((p)))
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#endif
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/* op r, [addr] */
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static void emit_rma(ASMState *as, x86Op xo, Reg rr, const void *addr)
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{
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MCode *p = as->mcp;
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*(int32_t *)(p-4) = ptr2addr(addr);
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#if LJ_64
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p[-5] = MODRM(XM_SCALE1, RID_ESP, RID_EBP);
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as->mcp = emit_opm(xo, XM_OFS0, rr, RID_ESP, p, -5);
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#else
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as->mcp = emit_opm(xo, XM_OFS0, rr, RID_EBP, p, -4);
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#endif
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}
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/* op r, [base+ofs] */
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static void emit_rmro(ASMState *as, x86Op xo, Reg rr, Reg rb, int32_t ofs)
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{
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MCode *p = as->mcp;
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x86Mode mode;
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if (ra_hasreg(rb)) {
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if (ofs == 0 && (rb&7) != RID_EBP) {
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if (LJ_GC64 && rb == RID_RIP) {
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mode = XM_OFS0;
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p -= 4;
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*(int32_t *)p = ofs;
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} else if (ofs == 0 && (rb&7) != RID_EBP) {
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mode = XM_OFS0;
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} else if (checki8(ofs)) {
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*--p = (MCode)ofs;
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@@ -202,6 +207,11 @@ static void emit_mrm(ASMState *as, x86Op xo, Reg rr, Reg rb)
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*--p = MODRM(XM_SCALE1, RID_ESP, RID_EBP);
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rb = RID_ESP;
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#endif
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} else if (LJ_GC64 && rb == RID_RIP) {
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lua_assert(as->mrm.idx == RID_NONE);
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mode = XM_OFS0;
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p -= 4;
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*(int32_t *)p = as->mrm.ofs;
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} else {
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if (as->mrm.ofs == 0 && (rb&7) != RID_EBP) {
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mode = XM_OFS0;
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@@ -241,10 +251,6 @@ static void emit_gmrmi(ASMState *as, x86Group xg, Reg rb, int32_t i)
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/* -- Emit loads/stores --------------------------------------------------- */
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/* Instruction selection for XMM moves. */
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#define XMM_MOVRR(as) ((as->flags & JIT_F_SPLIT_XMM) ? XO_MOVSD : XO_MOVAPS)
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#define XMM_MOVRM(as) ((as->flags & JIT_F_SPLIT_XMM) ? XO_MOVLPD : XO_MOVSD)
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/* mov [base+ofs], i */
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static void emit_movmroi(ASMState *as, Reg base, int32_t ofs, int32_t i)
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{
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@@ -259,8 +265,8 @@ static void emit_movmroi(ASMState *as, Reg base, int32_t ofs, int32_t i)
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/* Get/set global_State fields. */
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#define emit_opgl(as, xo, r, field) \
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emit_rma(as, (xo), (r), (void *)&J2G(as->J)->field)
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#define emit_getgl(as, r, field) emit_opgl(as, XO_MOV, (r), field)
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#define emit_setgl(as, r, field) emit_opgl(as, XO_MOVto, (r), field)
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#define emit_getgl(as, r, field) emit_opgl(as, XO_MOV, (r)|REX_GC64, field)
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#define emit_setgl(as, r, field) emit_opgl(as, XO_MOVto, (r)|REX_GC64, field)
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#define emit_setvmstate(as, i) \
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(emit_i32(as, i), emit_opgl(as, XO_MOVmi, 0, vmstate))
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@@ -268,10 +274,12 @@ static void emit_movmroi(ASMState *as, Reg base, int32_t ofs, int32_t i)
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/* mov r, i / xor r, r */
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static void emit_loadi(ASMState *as, Reg r, int32_t i)
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{
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/* XOR r,r is shorter, but modifies the flags. This is bad for HIOP. */
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/* XOR r,r is shorter, but modifies the flags. This is bad for HIOP/jcc. */
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if (i == 0 && !(LJ_32 && (IR(as->curins)->o == IR_HIOP ||
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(as->curins+1 < as->T->nins &&
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IR(as->curins+1)->o == IR_HIOP)))) {
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IR(as->curins+1)->o == IR_HIOP))) &&
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!((*as->mcp == 0x0f && (as->mcp[1] & 0xf0) == XI_JCCn) ||
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(*as->mcp & 0xf0) == XI_JCCs)) {
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emit_rr(as, XO_ARITH(XOg_XOR), r, r);
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} else {
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MCode *p = as->mcp;
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@@ -283,9 +291,21 @@ static void emit_loadi(ASMState *as, Reg r, int32_t i)
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}
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}
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#if LJ_GC64
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#define dispofs(as, k) \
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((intptr_t)((uintptr_t)(k) - (uintptr_t)J2GG(as->J)->dispatch))
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#define mcpofs(as, k) \
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((intptr_t)((uintptr_t)(k) - (uintptr_t)as->mcp))
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#define mctopofs(as, k) \
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((intptr_t)((uintptr_t)(k) - (uintptr_t)as->mctop))
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/* mov r, addr */
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#define emit_loada(as, r, addr) \
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emit_loadu64(as, (r), (uintptr_t)(addr))
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#else
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/* mov r, addr */
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#define emit_loada(as, r, addr) \
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emit_loadi(as, (r), ptr2addr((addr)))
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#endif
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#if LJ_64
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/* mov r, imm64 or shorter 32 bit extended load. */
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@@ -297,6 +317,15 @@ static void emit_loadu64(ASMState *as, Reg r, uint64_t u64)
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MCode *p = as->mcp;
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*(int32_t *)(p-4) = (int32_t)u64;
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as->mcp = emit_opm(XO_MOVmi, XM_REG, REX_64, r, p, -4);
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#if LJ_GC64
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} else if (checki32(dispofs(as, u64))) {
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emit_rmro(as, XO_LEA, r|REX_64, RID_DISPATCH, (int32_t)dispofs(as, u64));
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} else if (checki32(mcpofs(as, u64)) && checki32(mctopofs(as, u64))) {
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/* Since as->realign assumes the code size doesn't change, check
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** RIP-relative addressing reachability for both as->mcp and as->mctop.
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*/
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emit_rmro(as, XO_LEA, r|REX_64, RID_RIP, (int32_t)mcpofs(as, u64));
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#endif
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} else { /* Full-size 64 bit load. */
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MCode *p = as->mcp;
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*(uint64_t *)(p-8) = u64;
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@@ -308,13 +337,89 @@ static void emit_loadu64(ASMState *as, Reg r, uint64_t u64)
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}
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#endif
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/* movsd r, [&tv->n] / xorps r, r */
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static void emit_loadn(ASMState *as, Reg r, cTValue *tv)
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/* op r, [addr] */
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static void emit_rma(ASMState *as, x86Op xo, Reg rr, const void *addr)
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{
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if (tvispzero(tv)) /* Use xor only for +0. */
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emit_rr(as, XO_XORPS, r, r);
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else
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emit_rma(as, XMM_MOVRM(as), r, &tv->n);
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#if LJ_GC64
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if (checki32(dispofs(as, addr))) {
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emit_rmro(as, xo, rr, RID_DISPATCH, (int32_t)dispofs(as, addr));
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} else if (checki32(mcpofs(as, addr)) && checki32(mctopofs(as, addr))) {
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emit_rmro(as, xo, rr, RID_RIP, (int32_t)mcpofs(as, addr));
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} else if (!checki32((intptr_t)addr)) {
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Reg ra = (rr & 15);
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if (xo != XO_MOV) {
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/* We can't allocate a register here. Use and restore DISPATCH. Ugly. */
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uint64_t dispaddr = (uintptr_t)J2GG(as->J)->dispatch;
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uint8_t i8 = xo == XO_GROUP3b ? *as->mcp++ : 0;
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ra = RID_DISPATCH;
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if (checku32(dispaddr)) {
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emit_loadi(as, ra, (int32_t)dispaddr);
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} else { /* Full-size 64 bit load. */
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MCode *p = as->mcp;
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*(uint64_t *)(p-8) = dispaddr;
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p[-9] = (MCode)(XI_MOVri+(ra&7));
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p[-10] = 0x48 + ((ra>>3)&1);
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p -= 10;
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as->mcp = p;
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}
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if (xo == XO_GROUP3b) emit_i8(as, i8);
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}
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emit_rmro(as, xo, rr, ra, 0);
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emit_loadu64(as, ra, (uintptr_t)addr);
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} else
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#endif
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{
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MCode *p = as->mcp;
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*(int32_t *)(p-4) = ptr2addr(addr);
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#if LJ_64
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p[-5] = MODRM(XM_SCALE1, RID_ESP, RID_EBP);
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as->mcp = emit_opm(xo, XM_OFS0, rr, RID_ESP, p, -5);
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#else
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as->mcp = emit_opm(xo, XM_OFS0, rr, RID_EBP, p, -4);
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#endif
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}
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}
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/* Load 64 bit IR constant into register. */
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static void emit_loadk64(ASMState *as, Reg r, IRIns *ir)
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{
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Reg r64;
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x86Op xo;
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const uint64_t *k = &ir_k64(ir)->u64;
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if (rset_test(RSET_FPR, r)) {
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r64 = r;
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xo = XO_MOVSD;
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} else {
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r64 = r | REX_64;
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xo = XO_MOV;
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}
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if (*k == 0) {
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emit_rr(as, rset_test(RSET_FPR, r) ? XO_XORPS : XO_ARITH(XOg_XOR), r, r);
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#if LJ_GC64
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} else if (checki32((intptr_t)k) || checki32(dispofs(as, k)) ||
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(checki32(mcpofs(as, k)) && checki32(mctopofs(as, k)))) {
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emit_rma(as, xo, r64, k);
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} else {
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if (ir->i) {
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lua_assert(*k == *(uint64_t*)(as->mctop - ir->i));
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} else if (as->curins <= as->stopins && rset_test(RSET_GPR, r)) {
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emit_loadu64(as, r, *k);
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return;
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} else {
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/* If all else fails, add the FP constant at the MCode area bottom. */
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while ((uintptr_t)as->mcbot & 7) *as->mcbot++ = XI_INT3;
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*(uint64_t *)as->mcbot = *k;
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ir->i = (int32_t)(as->mctop - as->mcbot);
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as->mcbot += 8;
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as->mclim = as->mcbot + MCLIM_REDZONE;
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lj_mcode_commitbot(as->J, as->mcbot);
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}
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emit_rmro(as, xo, r64, RID_RIP, (int32_t)mcpofs(as, as->mctop - ir->i));
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#else
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} else {
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emit_rma(as, xo, r64, k);
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#endif
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}
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}
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/* -- Emit control-flow instructions -------------------------------------- */
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@@ -416,8 +521,10 @@ static void emit_call_(ASMState *as, MCode *target)
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/* Use 64 bit operations to handle 64 bit IR types. */
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#if LJ_64
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#define REX_64IR(ir, r) ((r) + (irt_is64((ir)->t) ? REX_64 : 0))
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#define VEX_64IR(ir, r) ((r) + (irt_is64((ir)->t) ? VEX_64 : 0))
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#else
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#define REX_64IR(ir, r) (r)
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#define VEX_64IR(ir, r) (r)
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#endif
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/* Generic move between two regs. */
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@@ -427,25 +534,25 @@ static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
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if (dst < RID_MAX_GPR)
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emit_rr(as, XO_MOV, REX_64IR(ir, dst), src);
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else
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emit_rr(as, XMM_MOVRR(as), dst, src);
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emit_rr(as, XO_MOVAPS, dst, src);
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}
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/* Generic load of register from stack slot. */
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static void emit_spload(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
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/* Generic load of register with base and (small) offset address. */
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static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
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{
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if (r < RID_MAX_GPR)
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emit_rmro(as, XO_MOV, REX_64IR(ir, r), RID_ESP, ofs);
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emit_rmro(as, XO_MOV, REX_64IR(ir, r), base, ofs);
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else
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emit_rmro(as, irt_isnum(ir->t) ? XMM_MOVRM(as) : XO_MOVSS, r, RID_ESP, ofs);
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emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSD : XO_MOVSS, r, base, ofs);
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}
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/* Generic store of register to stack slot. */
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static void emit_spstore(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
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/* Generic store of register with base and (small) offset address. */
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static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
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{
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if (r < RID_MAX_GPR)
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emit_rmro(as, XO_MOVto, REX_64IR(ir, r), RID_ESP, ofs);
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emit_rmro(as, XO_MOVto, REX_64IR(ir, r), base, ofs);
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else
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emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSDto : XO_MOVSSto, r, RID_ESP, ofs);
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emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSDto : XO_MOVSSto, r, base, ofs);
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}
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/* Add offset to pointer. */
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@@ -453,9 +560,9 @@ static void emit_addptr(ASMState *as, Reg r, int32_t ofs)
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{
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if (ofs) {
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if ((as->flags & JIT_F_LEA_AGU))
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emit_rmro(as, XO_LEA, r, r, ofs);
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emit_rmro(as, XO_LEA, r|REX_GC64, r, ofs);
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else
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emit_gri(as, XG_ARITHi(XOg_ADD), r, ofs);
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emit_gri(as, XG_ARITHi(XOg_ADD), r|REX_GC64, ofs);
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}
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}
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